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Simulation is useful to prove designs.


Experience includes

  • PAL's/GAL's using abel
  • Lattice CPLDs - VHDL
  • FPGAs - Altera / Xilinx - VHDL/verilog
  • Used tools such as FPGA express, Maxplus, Renoir, Leonardo spectrum, simplify, XACT, Xilinx Design Manager.
  • Also considering using more vendor specific tools as a low cost solution to supporting the array of devices available.
  • see also Simulation
  •  Implementations: FIFO, queues, Pseudo random sequence, BERT generator, PLL/VCXO, fractional+normal Baud Rate Generators. Interrupt logic, decode, memory pools, monitoring filters, state machines, pipelines, protocols, CRCs….

 


Last Updated: February, 2006